Deep Submicron Delay Effects
Deep Submicron Delay Effects |
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| These discussions were abstracted from the book, Designus Maximus Unleashed, with the kind permission of Newnes, Woburn, MA, USA. Designus Maximus Unleashed rampages through a smorgasbord of contemporary electronics topics, ranging from design capture, logic synthesis, and digital simulation (logic, fault, and timing), through testing RAMs and ROMs, to the esoteric worlds of diamond substrates, genetic algorithms, and nanotechnology. |
| Part 1: The Evolution of Delay Specifications | ||
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back in the mists of time,
sometime after the Jurassic period when dinosaurs ruled the earth, say around the early
1980s, the lives of IC and ASIC designers were somewhat simpler than they are today. Delay specifications for the early (multi- micron) technologies were rudimentary at best. Consider the case of a simple 2-input AND gate, for which input-to-output databook delays were originally specified as being identical for all of the inputs and for both rising and falling transitions at the output (Figure 1). |
Figure 25-1: Delay
specifications have become |
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| As device geometries shrank, however, delay specifications became increasingly complex; first by differentiating delays for rising and falling output transitions, and later by specifying different delays for each input. Additionally, these early delays were typically of the form "X ns + Y ns/pF," which means a fixed delay associated with the gate itself combined with some additional delay caused by capacitive loading. As we will see, these forms of specification simply cannot handle the types of delay effects characteristic of deep- submicron technologies, not the least in the area of RLC interconnect delays as discussed later in this article. | ||
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These notes are abstracted Designus Maximus Unleashed Copyright Information |
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