Hello there and welcome to the PhizzyB Zone. In the future we'll be developing these pages to include a FAQ (Frequently Asked Questions), an online chat area, and much, much more.

Meanwhile, if you have any urgent questions or problems, please email us at support@maxmon.com and we will leap into action immediately (if not sooner).

One point of interest is that PhizzyB fan Don McBrien in Ireland has has discovered a bug in the PhizzyB Simulator (and the Beboputer Simulator). All of our documentation describes the SHR ("shift right") instruction as copying the MS bit back into itself.

This form of shift reflects an "arithmetic shift right" and this is the way it's supposed to work (and it IS the way that the real PhizzyB works). However, for some (as-yet-undetermined) reason, the PhizzyB Simulator actually performs a "logical shift right" which means that it shifts a zero into the MS bit.

The simplest fix is to force the real PhizzyB to act like the simulator. This can be achieved by following a SHR instruction with an AND as follows:

<instruction>
<instruction>
:
SHR
AND %01111111
:
<instruction>
<instruction>

This forces the MS bit to be a logic 0 (which is what the simulator does incorrectly/anyway). Unfortunately, forcing the simulator to perform an arithmetic shift like it's supposed to (and like the real PhizzyB does) is much more painful. There are several ways to achieve this -- one of the simplest to understand is to create a SHRA ("shift right arithmetic") subroutine as follows:

# Main body of program
<instruction>
<instruction>
:
JSR [SHRA]   # Instead of using a SHR instruction,
             # jump to a SHRA subroutine
:
<instruction>
<instruction>

In the subroutine (shown below) we use a JN ("Jump if negative") instruction to decide whether or not to set the MS bit to 1 as follows:

### Start of subroutine SHRA
SHRA:   JN [SHR1] # If MS bit is 1 jump to SHR1
SHR0:   SHR       # Otherwise just shift right (logical)
RTS               # Return from subroutine
SHR1:   SHR       # Shift right (logical)
OR %10000000      # Force MS Bit to 1
RTS               # Return from subroutine.
### End of subroutine SHRA

We hope to offer a simulator fix at some stage in the future (downloadable from the web) -- but this should provide a workable solution for the nonce.

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